1. Field of the Invention
This invention relates to semiconductor devices and more particularly to MOSFET devices and a method of manufacture thereof.
2. Description of Related Art
Shallow Trench Isolation (STI) region structures are often used in advanced integrated circuits. The STI technique provides higher device densities and better planarity than other isolation methods. However, STI has a disadvantage in terms of device characteristics. Because of the steep slope of the silicon (Si) sidewall adjacent to an STI structure, an applied gate voltage results in an enhanced electric field at the corner of the active area. The field is further enhanced if the STI is recessed so that the gate wraps around the corner. The resulting "corner device" shown in FIG. 1 has a lower threshold voltage than the main device, which can lead to a high "off" current and to variations in the threshold voltage of the transistor as described by Bryant et al, in "Characteristics of CMOS Device Isolation for the ULSI Age", IEDM Tech. Dig., pp. 671-674 (1994). FIG. 1 shows a sectional view of a prior art semiconductor device 10 formed on a P- doped silicon substrate on which is formed a gate oxide layer GOX above a channel CH. To the right of the gate oxide layer is an isolation region STI separated from the lightly doped P- substrate 12 by a sidewall SW which forms a corner CR with a radius r and a corner angle CA of .theta. with the lower surface of the gate oxide layer GOX. To the right of the corner CR is formed a wraparound WR depression in the surface of the isolation region STI. Upon the gate oxide layer GOX and the isolation region STI is formed a doped polysilicon layer PS which is to serve as a gate electrode of an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device. As stated in Bryant et al in the legend for FIG. 1 thereof, "The abrupt geometric step of an Ideal Isolation edge results in the separate conduction characteristic of the corner parasitic. Corner radius, sidewall corner angle, and gate wraparound impact conduction."
A number of solutions have been proposed to solve this problem. One method is to simply ensure that the surface of the STI is always above that of the silicon as described in K. Shibahara et al., "Trench Isolation with DEL(NABLA)-shaped Buried Oxide for 256 Mega-bit DRAMS" IEDM, (1992) p. 275. However, this can create topography that makes gate patterning more difficult. (Rails can be left along the sidewalls of the protruding STI.)
Another method is to implant the appropriate dopants (i.e., B (Boron) for an N-channel FET (NFET)) into the sidewalls of the trench to increase the threshold voltage along the sidewall. However, this requires an extra blockout mask.
The prior art listed below relates to methods of minimizing the effect of the corner device, either by corner rounding or by doing implants into the sidewalls of the trenches.
In Evans et al. European Patent No. 0 685 882 A1 the sidewalls of the trenches are implanted to adjust the threshold voltage of the corner device, similar to G. Fuse, et al., "A Practical Trench Isolation Technology with a Novel Planarization Process" IEDM 87, pp. 732-735 (1987); and P. C. Fazan and V. K. Matthews, "A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs", IEDM 93, pp. 57-60 (1993). The approach used by Evans depends on the isolation trench having sloping sidewalls. See the Abstract relative to threshold adjustment of isolation trench using doped sidewalls and bottom.
Horioka et al. U.S. Pat. No. 5,258,332 "Method of Manufacturing Semiconductor Devices Including Rounding of Corner Portions by Etching" and D. S. Wen, "Optimized Shallow Trench Isolation Structure and Its Process for Eliminating Shallow Trench Isolation-Induced Parasitic Effects" IBM Tech. Dis. Bull., pp. 276-277 (April, 1992) propose using corner rounding to control the corner device.
In principle, this is a good method but it can be difficult to control. Horoika also shows implantation into the sidewall, as well as the corner.
Manning U.S. Pat. No. 5,275,965 proposes using gated sidewalls in the isolation region. This structure could have a detrimental effect on yield due to the presence of a conductor in the isolation region. Furthermore this approach suffers from added wiring complexity and the need to bias the NFET and P-channel FET (PFET) isolation trenches at different voltage levels. In particular, see the Abstract; Col. 3, lines 32-37 and lines 51-56. The device includes a channel adjusted for threshold by implanting. Sidewalls of the trench are "gated" to prevent parasitic turn-on.
Erb et al. U.S. Pat. No. 5,212,106 and Erb et al. U.S. Pat. No. 5,215,937 use sidewalls to make an threshold voltage implant that is self-aligned to the gate conductor. However, it is not self-aligned to the isolation region (as they point out) and therefore cannot be used to adjust the corner device. The reference mentions doing implants into the sidewalls of the trenches to control the corner device. Erb does not anticipate the problem solved by our invention.
Yasaitis U.S. Pat. No. 4,722,910 describes a sidewall formed along the isolation region to make a borderless contact. This has nothing to do with controlling a corner device.
Akamatsu et al. U.S. Pat. No. 5,396,096 describes a masked implant used to protect the edge of the isolation region from high electric fields. This is done after gate patterning and does not affect the corner device (but Akamatsu et al. does not anticipate the problem solved by the present invention.)
Burger et al. U.S. Pat. No. 5,482,878 describes threshold adjustment of implants using blocking masks.
Dhong et al. U.S. Pat. No. 5,021,355; Anderson U.S. Pat. No. 5,300,447; and Tanaka et al. U.S. Pat. No. 5,408,116 describe trench transistor devices.
Threshold adjustment using geometry of isolation trench corners is described in the Wen TDB article, Tanaka et al. U.S. Pat. No. 5,408,116 and Horioka et al. U.S. Pat. No. 5,258,332 referred to above.
Different implant levels on device using LOCOS isolation regions are discussed in U.S. Pat. No. 5,396,096 (Akamatsu et al.) and U.S. Pat. No. 4,722,910 (Yasaitis).
Using the corner of the trench gate to provide dopant is described in U.S. Pat. No. 5,300,447 (Anderson) and U.S. Pat. No. 5,021,355 (Dhong et al.).